A semiconductor integrated circuit (“IC”) is generally susceptible to an electrostatic discharge (“ESD”) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to the IC. It is known that the susceptibility of a device to an ESD event may be determined by testing for one of three models, Human Body Model (HBM), Machines Model (MM), and Charged-Device Model (CDM).
The ESD Association Standard for the Development of an Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Device), ANSI/ESD-S20.20-1999 (Aug. 4, 1999), provides for ESD sensitivity testings for each of the three models. The HBM model represents the discharge from the fingertip of a standing individual delivered to conductive leads of a device. FIG. 1 shows an HBM model ESD test circuit, modeled by a 100 picofarad (pF) capacitor, representing the effective capacitance of the human body, discharged through a switching component and 1,500 ohm series resistor, representing the effective resistance of the human body, into the device under tests. The discharge is a double exponential waveform with a rise time of 2-10 nanoseconds (nS) and a pulse duration of approximately 150 nS.
The MM model represents a rapid discharge from items such as a charged board assembly, charged cables, or the conduction arm of an automatic tester. The effective capacitance is approximately 200 pF discharged through a 500 nanohenry (nH) inductor directly into the device because the effective resistance of the machine is approximately zero. The discharge is a sinusoidal decaying waveform having a peak current of approximately 3.8 amperes (A) with a resonant frequency of approximately 16 MHz.
The CDM model is a phenomenon when a device acquires charge through frictional or electrostatic induction processes and then abruptly touches a grounded object or surface. Most of the charge is accumulated in a substrate, including a base, a bulk or a well, of the device, and is uniformly distributed in the substrate. Unlike the HBM model and the MM model, the CDM model includes situations where the device itself becomes charged and discharges to ground. The rise time is generally less than 200 picoseconds (pS), and the entire ESD event can take place in less than 2 nS. Current levels can reach several tens of amperes during discharge.
FIG. 2 is a plot showing the characteristics of HBM, MM and CDM discharges. Referring to FIG. 2, the CDM discharge reaches a peak current of approximately 15 A in less than 1 nS, and the discharge is complete within approximately 10 nS.
Many schemes have been implemented to protect an IC from the three types of ESD events. Examples of conventional ESD protection schemes include an HBM/MM ESD clamp and a CDM ESD clamp. FIG. 3 shows a scheme using a PMOS transistor Mp1a and an NMOS transistor Mn1b as a CDM ESD clamp to conduct electrostatic charges, accumulated in the substrate of transistors Mp5 or Mn5, to an input pad as the input pad is grounded. Incorporating transistors Mp1a and Mn1b into the scheme shown in FIG. 3 for CDM ESD protection is necessary because the HBM/MM ESD clamp is unable to respond to a CDM event in time before the accumulated CDM charge destroys a thin gate oxide of transistors Mn5 or Mp5.
FIG. 4 shows a scheme using diodes D1a, D1b, D2a and D2b as a CDM ESD clamp to conduct CDM charges, and having an HBM/MM ESD clamp similar to that shown in FIG. 3. The diodes are connected by different power lines for possible additional ESD discharging paths.
FIG. 5 is a reproduction of FIG. 8 of U.S. Pat. No. 5,901,022 (hereinafter “the '022 patent”) to Ker, one of the inventors of the present invention, entitled “Charged Device Mode ESD Protection Circuit.” The '022 patent discloses an ESD protection circuit having an HBM/MM ESD clamp that uses an inductor L to couple to an input stage including transistors Mp and Mn. Inductor L functions to protect the internal circuit from a CDM ESD event. Since inductor L may be disposed under an input pad, the layout area of the ESD protection circuit is not increased.
With the advance of semiconductor technology into a deep sub-micron era, the conventional ESD protection schemes, such as those described above, may no longer be effective in protecting gate oxides that are as thin as 4 na iiefes nanometers (tim) or less from a CDM ESD event. It is desirable to provide an CDM ESD protection circuit that is able to quickly conduct CDM charges to ground during a CDM ESD event.